Principal Electrical Design Engineer
Astera Labs · San Jose, California, United States · $185k–$240k
Posted by Astera Labs on their careers site · View the original posting
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Mid level
Open 66 days
The posting, as Astera Labs wrote it
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
Job Description
Principal Electrical Design Engineer
Board Hardware Engineering
About the Role
We are seeking a Principal Electrical Design Engineer to define and drive the architecture, design, and technical strategy for advanced board-level hardware across next-generation networking and high-performance connectivity platforms. This role encompasses complex hardware systems including chassis boards, NIC cards, PCIe Gen6 platforms, and 800G Ethernet products.
This is a principal-level technical leadership role requiring deep domain expertise, strategic vision, and organizational influence. You will set the technical direction for board architecture, establish design methodologies, drive innovation in high-speed system design, and serve as the top technical authority across multiple programs. You will partner with and influence silicon, SI/PI, mechanical, firmware, manufacturing, system, and executive teams to deliver industry-leading products from concept through production and beyond.
Key Responsibilities
Technical Strategy and Architecture Leadership
- Define and own the board-level hardware architecture and technical roadmap across multiple product lines and platform generations
- Establish design standards, methodologies, and best practices that scale across the hardware engineering organization
- Drive architectural tradeoff decisions for complex multi-layer PCBs integrating high-speed digital, analog, and mixed-signal circuitry, balancing performance, cost, schedule, and manufacturability
- Get involved and drive discussions on stack-up strategy, impedance optimization and other SI relates development work
- Own power delivery architecture strategy including multi-rail regulation topologies, advanced sequencing schemes, transient response optimization, protection philosophies, and power budgeting across platform generations
- Define and evolve hardware implementation strategies for management and control interfaces such as I2C, SPI, GPIO, MDIO, and debug and observability architectures
Electrical Design Ownership
- Own schematic capture and board-level design for complex multi-layer PCBs with high-speed digital, analog, and mixed-signal circuitry
- Serve
[…]
o or OrCAD
- Proven track record leading hardware bring-up and debug of complex platforms using oscilloscopes, protocol analyzers, and advanced lab instrumentation
- Demonstrated ability to lead cross-functional teams and influence technical direction across organizational boundaries from architecture through validation and production
- Strong track record of mentoring engineers and elevating team capabilities
Preferred Qualifications
- Experience defining architecture for NIC cards, accelerator cards, or other PCIe add-in card platforms across multiple generations
- Experience leading server chassis or system board design programs in dense, thermally constrained, high-availability environments
- Deep expertise with 800G Ethernet and emerging 1.6T electrical interfaces and system integration challenges
- Experience architecting solutions using retimers, redrivers, advanced clocking architectures, and high-speed interconnect subsystems
- Expertise in compliance and validation workflows for PCIe and Ethernet platforms, including contributions to industry specifications or standards bodies
- Experience driving contract manufacturer relationships, production ramp strategies, and yield optimization for complex hardware products
- Scripting and automation proficiency in Python or similar languages for lab automation, measurement analysis, hardware characterization workflows, and design flow optimization
- Experience influencing product strategy and roadmap decisions at the organizational level
Base pay range for this role is $185,000 - $240,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.