Chip design and verification (ASIC) jobs

The newest

• Principal Design Verification Engineer (AI Fabric Switches) · Astera Labs · San Jose, California, United States
• Physical Design Engineer, ML4PD · Tenstorrent · Austin, Texas, United States
• Senior Digital Design Verification Engineer - Hardware · NVIDIA · US, CA, Santa Clara
• Principal Analog/Mixed-Signal ASIC Design Engineer · Taara · Sunnyvale, CA
• Lead Analog/Mixed-Signal ASIC Design Engineer · Taara · Sunnyvale, CA
• ASIC Design Engineer · NVIDIA · US, CA, Santa Clara
• Senior Design Verification Engineer · Micron · Minneapolis, MN
• Design Verification Engineer · Broadcom · USA-CA San Jose Innovation Drive
• Design Verification Engineer (2027 New College Graduate) · GlobalFoundries · USA - Texas - Richardson
• Design Verification Engineer Intern (Summer 2027) · GlobalFoundries · USA - Texas - Richardson
• Staff Design Verification Engineer – SoC and eFPGA · Analog Devices · US, TX, Austin, Plaza on the Lake
• Principal SoC RTL Engineer · Ambiq Micro, Inc. · Austin, Texas, United States
• Principal Physical Design Engineer, STA · Broadcom · USA-CA San Jose Innovation Drive
• Physical Design Engineer · Broadcom · USA-CA San Jose Innovation Drive
• Physical Design Engineer · Broadcom · USA-CA San Jose Innovation Drive
• Principal Physical Design Engineer · Broadcom · USA-CA San Jose Innovation Drive
• ASIC Design Engineer · Broadcom · USA-Colorado-Fort Collins-4380 Ziegler Road
• CPU Physical Design Engineer · Intel · US, Texas, Austin
• Physical Design Engineer, New Grad · SambaNova Systems · San Jose, California, United States
• Design Verification Engineer, New Grad · SambaNova Systems · San Jose, California, United States
• Principal Design Verification Engineer- SerDes/PHY IP · Astera Labs · San Jose, California, United States
• Senior Physical Design Engineer · Broadcom · USA-CA San Jose Innovation Drive
• Senior Design Verification Engineer · Astera Labs · San Jose, California, United States
• Design Verification Engineer - Compute · MatX · Mountain View (HQ) or Remote
• Senior ASIC Design Engineer - DSP/Analog/SerDes · Celero Communications, Inc. · Ottawa, Ontario, Canada
• Senior ASIC Design Engineer - DSP/Analog/SerDes · Celero Communications, Inc. · Irvine, CA
• Senior ASIC Design Engineer - DSP/Analog/SerDes · Celero Communications, Inc. · San Jose, CA
• Physical Design Engineer · Voltai · Palo Alto Office
• ASIC Design Engineer (Silicon Engineering) · SpaceX · Palo Alto, CA
• Physical Design Engineer · SK hynix memory solutions America Inc. · San Jose
• Digital ASIC Design Engineer · AttoTude · Nuremberg, Germany
• Substation Physical Design Engineer · Halker Consulting · Remote
• AI Silicon, Physical Design Engineer · Unconventional, Inc. · Mountain View, CA I Remote
• Senior Design Verification Engineer · Astera Labs · San Jose, California, United States
• Sr. Staff / Principal Physical Design Engineer · SK hynix memory solutions America Inc. · San Jose
• Senior or Staff Design Verification Engineer · Powerlattice Technologies Inc. · HQ - Vancouver, WA
• Physical Design Engineer, Timing · Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
• Principal Physical Design Engineer · Celero Communications, Inc. · San Jose, CA
• Principal Physical Design Engineer · Celero Communications, Inc. · Irvine, CA
• RTL Engineer Memory Subsystem · Velaura · Santa Clara, CA