Chip design and verification (ASIC) jobs in the Bay Area

The newest

• Principal Design Verification Engineer (AI Fabric Switches) · Astera Labs · San Jose, California, United States
• Senior Digital Design Verification Engineer - Hardware · NVIDIA · US, CA, Santa Clara
• Principal Analog/Mixed-Signal ASIC Design Engineer · Taara · Sunnyvale, CA
• Lead Analog/Mixed-Signal ASIC Design Engineer · Taara · Sunnyvale, CA
• ASIC Design Engineer · NVIDIA · US, CA, Santa Clara
• Design Verification Engineer · Broadcom · USA-CA San Jose Innovation Drive
• Principal Physical Design Engineer, STA · Broadcom · USA-CA San Jose Innovation Drive
• Physical Design Engineer · Broadcom · USA-CA San Jose Innovation Drive
• Physical Design Engineer · Broadcom · USA-CA San Jose Innovation Drive
• Principal Physical Design Engineer · Broadcom · USA-CA San Jose Innovation Drive
• Physical Design Engineer, New Grad · SambaNova Systems · San Jose, California, United States
• Design Verification Engineer, New Grad · SambaNova Systems · San Jose, California, United States
• Principal Design Verification Engineer- SerDes/PHY IP · Astera Labs · San Jose, California, United States
• Senior Physical Design Engineer · Broadcom · USA-CA San Jose Innovation Drive
• Senior Design Verification Engineer · Astera Labs · San Jose, California, United States
• Design Verification Engineer - Compute · MatX · Mountain View (HQ) or Remote
• Senior ASIC Design Engineer - DSP/Analog/SerDes · Celero Communications, Inc. · San Jose, CA
• Physical Design Engineer · Voltai · Palo Alto Office
• ASIC Design Engineer (Silicon Engineering) · SpaceX · Palo Alto, CA
• Physical Design Engineer · SK hynix memory solutions America Inc. · San Jose
• AI Silicon, Physical Design Engineer · Unconventional, Inc. · Mountain View, CA I Remote
• Senior Design Verification Engineer · Astera Labs · San Jose, California, United States
• Sr. Staff / Principal Physical Design Engineer · SK hynix memory solutions America Inc. · San Jose
• Physical Design Engineer, Timing · Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
• Principal Physical Design Engineer · Celero Communications, Inc. · San Jose, CA
• RTL Engineer Memory Subsystem · Velaura · Santa Clara, CA
• Midcore Design Verification Engineer · Tenstorrent · Santa Clara, California, United States; Spain
• SoC Design Verification Engineer · Velaura · Santa Clara, CA
• Physical Design Engineer · OpenAI · San Francisco
• Front End Design Verification Engineer · Tenstorrent · Santa Clara, California, United States; Spain
• Physical Design Engineer · Delos Data Inc · Palo Alto
• Senior RTL Engineer, IO Die and Interconnect IP · Samsung Semiconductor · San Jose, California, United States
• Design Verification Engineer- AI Accelerator · Velaura · Santa Clara, CA
• Design Verification Engineer- CPU · Velaura · Santa Clara, CA
• Senior RTL Engineer, Memory Centric Computing · Samsung Semiconductor · San Jose, California, United States
• Senior Physical Design Engineer · Samsung Semiconductor · San Jose, California, United States
• Design Verification Engineer · SambaNova Systems · San Jose, California, United States
• Staff Design Verification Engineer · Cerebras Systems · Sunnyvale, CA
• Senior Staff Design Verification Engineer · Cerebras Systems · Sunnyvale, CA
• Mid Level ASIC Design Engineer · Tensordyne · Sunnyvale, CA