Jobs using SystemVerilog
74 open · Open roles whose own postings name SystemVerilog
The newest
- Validation and Verification Engineer, Aviation Engineering · Skyryse · El Segundo, CA
- Principal PCS/PMA RTL Design Engineer · Astera Labs · San Jose, California, United States
- Technical Lead Digital Design Engineer · Astera Labs · San Jose, California, United States
- Hardware Engineers: RTL Implementation and Evaluation Workflows · Terac · United States
- ASIC Architect · Delos Data Inc · Palo Alto
- Principal SoC RTL Engineer · Ambiq Micro, Inc. · Austin, Texas, United States
- Forward Deployed Engineer · ChipAgents · San Jose
- Hardware Engineer II - Design Verification · HPR · Needham, MA
- Design Verification Engineer, New Grad · SambaNova Systems · San Jose, California, United States
- Principal Design Verification Engineer- SerDes/PHY IP · Astera Labs · San Jose, California, United States
- Senior Design Verification Engineer · Astera Labs · San Jose, California, United States
- Design Verification Engineer - Compute · MatX · Mountain View (HQ) or Remote
- Senior ASIC Design Engineer - DSP/Analog/SerDes · Celero Communications, Inc. · Ottawa, Ontario, Canada
- Senior ASIC Design Engineer - DSP/Analog/SerDes · Celero Communications, Inc. · Irvine, CA
- Senior ASIC Design Engineer - DSP/Analog/SerDes · Celero Communications, Inc. · San Jose, CA
- RTL Design Engineer · Delos Data Inc · Palo Alto
- Microarchitect and RTL Designer - Compute · MatX · Mountain View (HQ) or Remote
- RTL Design Engineer · Voltai · Palo Alto Office
- Staff ML Accelerator Architect · Waymo · Mountain View, CA, USA; New York, New York, USA
- ASIC Architect · Normal Computing Corporation · Mountain View
- Product Manager · Normal Computing Corporation · New York
- ASIC Design Engineer (Silicon Engineering) · SpaceX · Palo Alto, CA
- Electrical Engineer - FPGA Firmware · Star Catcher · Jacksonville, Florida, United States
- Methodology Engineer (Silicon) · MatX · Mountain View (HQ) or Remote
- Digital ASIC Design Engineer · AttoTude · Nuremberg, Germany
- FPGA/Firmware Engineer · Quest Defense Systems & Solutions, Inc. · Cedar Rapids, IA
- FPGA/ASIC Design Engineer (Silicon Engineering) · SpaceX · Irvine, CA
- FPGA/ASIC Design Engineer (Silicon Engineering) · SpaceX · Redmond, WA
- Senior Design Verification Engineer · Astera Labs · San Jose, California, United States
- Tech Lead Engineer, Design Verification · Astera Labs · San Jose, California, United States
- FPGA Associate (Winter 2027) · Astranis · San Francisco
- FPGA Associate (Summer 2027) · Astranis · San Francisco
- Hardware Machine Learning PhD Research Internship · IMC Trading · Chicago, United States
- Senior or Staff Design Verification Engineer · Powerlattice Technologies Inc. · HQ - Vancouver, WA
- Software Engineer, AI Tooling · MatX · Mountain View
- Midcore Design Verification Engineer · Tenstorrent · Santa Clara, California, United States; Spain
- Front End Design Verification Engineer · Tenstorrent · Santa Clara, California, United States; Spain
- Software Engineer, AI for Chip Design · OpenAI · San Francisco
- Sr. Staff Engineer, CPU (Front-End) Verification · Tenstorrent · Austin, Texas, United States; Santa Clara, California, United States
- Silicon Validation Engineer, Software · Etched · San Jose